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MC100LVE210 3.3V ECL Dual 1:4, 1:5 Differential Fanout Buffer
Description
The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features fully differential clock paths to minimize both device and system skew. The dual buffer allows for the fanout of two signals through a single chip, thus reducing the skew between the two fundamental signals from a part-to-part skew down to an output-to-output skew. This capability reduces the skew by a factor of 4 as compared to using two LVE111's to accomplish the same task. To ensure that the tight skew specification is met it is necessary that both sides of the differential output are identically terminated, even if only one side is being used. In most applications all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used it is necessary to terminate at least the output pairs adjacent to the output pair being used in order to maintain minimum skew. Failure to follow this guideline will result in small degradations of propagation delay (on the order of 10-20 ps) of the outputs being used, while not catastrophic to most designs this will result in an increase in skew. Note that the package corners isolate outputs from one another such that the guideline expressed above holds only for outputs on the same side of the package. The MC100LVE210, as with most ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the LVE210 to be used for high performance clock distribution in +3.3 V systems. Designers can take advantage of the LVE210's performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage of VCC - 2.0 V will need to be provided. For more information on using PECL, designers should refer to Application Note AN1406/D. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
Features
http://onsemi.com MARKING DIAGRAM*
1 28
MC100LVE210G AWLYYWW PLCC-28 FN SUFFIX CASE 776
A WL YY WW G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.
* * * * * * * *
200 ps Part-to-Part Skew 50 ps Typical Output-to-Output Skew The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V Internal Input Pulldown Resistors Q Output will Default LOW with Inputs Open or at VEE Pb-Free Packages are Available*
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
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December, 2006 - Rev. 7
Publication Order Number: MC100LVE210/D
MC100LVE210
Qa0 Qa0 Qa1 VCCO Qa1 Qa2 Qa2 25 VEE VBB CLKa VCC CLKa CLKb CLKb 26 27 28 1 2 3 4 5 6 7 8 9 10 11 24 23 22 21 20 19 18 17 16 Qa3 Qa3 Qa2 Qb0 VCCO Qb0 Qb0 Qb1 Qb1 CLKb CLKb Qb0 Qb1 Qb1 Qb2 Qb2 Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. Qb3 Qb3 Qa2 Qa3 Qa3 CLKa CLKa Qa0 Qa0 Qa1 Qa1
Pinout: 28-Lead PLCC (Top View)
15 14 13 12
Qb4 Qb4 Qb3 VCCO Qb3 Qb2 Qb2
Figure 1. Pinout Assignment
Qb4
Table 1. PIN DESCRIPTION
Pin CLKa, CLKa Function ECL Differential Input Pairs ECL Differential Input Pairs ECL Differential Outputs ECL Differential Outputs VBB
Qb4
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CLKb, CLKb Qa0:3, Qa0:3 Qb0:3, Qb0:3 VBB Reference Voltage Output Positive Supply VCC, VCCO VEE Negative Supply
Figure 2. Logic Diagram
Table 2. ATTRIBUTES
Characteristic Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Pb Pkg Level 1
Value 50 kW N/A > 2 kV > 200 V Pb-Free Pkg Level 3
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) PLCC-28 Flammability Rating Transistor Count Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in 179
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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MC100LVE210
Table 3. MAXIMUM RATINGS
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 lfpm 500 lfpm Standard Board <2 to 3 sec @ 248C PLCC-28 PLCC-28 PLCC-28 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI v VCC VI w VEE Condition 2 Rating 8 to 0 -8 to 0 6 to 0 -6 to 0 50 100 0.5 -40 to +85 -65 to +150 63.5 43.5 22 to 26 5% 265 Unit V V V V mA mA mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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MC100LVE210
Table 4. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V (Note 2)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 7) Input HIGH Current Input LOW Current 0.5 2215 1470 2135 1490 1.92 1.8 2295 1605 Min Typ Max 55 2420 1745 2420 1825 2.04 2.9 150 0.5 2275 1490 2135 1490 1.92 1.8 2345 1595 Min 25C Typ Max 55 2420 1680 2420 1825 2.04 2.9 150 0.5 2275 1490 2135 1490 1.92 1.8 2345 1595 Min 85C Typ Max 65 2420 1680 2420 1825 2.04 2.9 150 Unit mA mV mV mV mV V V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary 0.3 V. 3. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 4. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. VIHCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
Table 5. LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = -3.3 V (Note 5)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 6) Output LOW Voltage (Note 6) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 7) Input HIGH Current Input LOW Current 0.5 -1085 -1830 -1165 -1810 -1.38 -1.5 -1005 -1695 Min Typ Max 55 -880 -1555 -880 -1475 -1.26 -0.4 150 0.5 -1025 -1810 -1165 -1810 -1.38 -1.5 -955 -1705 Min 25C Typ Max 55 -880 -1620 -880 -1475 -1.26 -0.4 150 0.5 -1025 -1810 -1165 -1810 -1.38 -1.5 -955 -1705 Min 85C Typ Max 65 -880 -1620 -880 -1475 -1.26 -0.4 150 Unit mA mV mV mV mV V V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary 0.3 V. 6. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 7. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. VIHCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
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MC100LVE210
Table 6. AC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = -3.3 V (Note 8)
-40C Symbol fmax tPLH tPHL tskew Characteristic Maximum Toggle Frequency Propagation Delay to Output IN (Differential) (Note 9) IN (Single-Ended) (Note 10) Within-Device Skew (Note 11) Qa to Qb Qa to Qa, Qb to Qb Part-to-Part Skew (Diff) Cycle-to-Cycle Jitter Input Swing (Note 12) Output Rise/Fall Time (20%-80%) 500 200 475 400 50 50 <1 1000 600 500 200 Min Typ 700 875 850 75 75 200 500 450 50 30 <1 1000 600 500 200 Max Min 25C Typ 700 900 900 75 50 200 500 450 50 30 <1 1000 600 Max Min 85C Typ 700 900 900 75 50 200 ps Max Unit GHz ps
tJITTER VPP tr/tf
ps mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. VEE can vary 0.3 V. 9. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 10. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the crossing point of the differential output signals. 11. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device. 12. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for the LVE210 as a differential input as low as 50 mV will still produce full ECL levels at the output.
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MC100LVE210
Zo = 50 W
Q Driver Device Q
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device MC100LVE210FN MC100LVE210FNG MC100LVE210FNR2 MC100LVE210FNR2G Package PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) Shipping 37 Units / Rail 37 Units / Rail 500 Tape & Reel 500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC100LVE210
PACKAGE DIMENSIONS
PLCC-28 FN SUFFIX PLASTIC PACKAGE CASE 776-02 ISSUE E
B -N- Y BRK
0.007 (0.180) U
M
T L-M
M
S
N
S S
0.007 (0.180)
T L-M
N
S
D Z -L- -M-
W
28 1
D
X VIEW D-D
G1
V
0.010 (0.250)
S
T L-M
S
N
S
A Z R C
0.007 (0.180) 0.007 (0.180) E
M M
T L-M T L-M
S S
N N
S S
H
0.007 (0.180)
M
T L-M
S
N
S
K1 0.004 (0.100) -T- SEATING
PLANE
G G1 0.010 (0.250)
S
J
K F VIEW S 0.007 (0.180)
M
VIEW S T L-M
S
T L-M
S
N
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10_ 0.410 0.430 0.040 ---
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10_ 10.42 10.92 1.02 ---
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MC100LVE210
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC100LVE210/D

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